Clock signals are used in virtually every integrated circuit (IC) and electronic system to control timing. For example, every time a rising edge occurs on a clock signal, all the flip-flops in a circuit might change state. Clearly, clocks are often heavily loaded signals, and can be bussed throughout a very large IC. Even with specially-designed global buffers, there is typically a delay between the clock edge received by the IC at the pad, and the clock edge received by the last-served flip-flop on the IC (i.e., between the “input clock signal” and the “destination clock signal”).
This delay, designated herein as td can cause difficulties in interfacing between Ics, or can simply slow down the overall system speed. Input data can be provided in synchronization with the input clock signal, while output data is typically provided in synchronization with the destination clock signal. Further, td often varies not only between different ICs, but on a single IC with temperature and voltage as well. It is highly desirable to have a circuit and method for synchronizing a destination clock signal with an input clock signal, so that the destination clock signals of various ICs can be commonly synchronized by synchronizing each destination clock signal to a common input clock signal.
This clock synchronization procedure is often performed using a phase-lock loop (PLL) or delay-lock loop (DLL). However, known PLLs and DLLs consume a great deal of silicon area. Additionally, PLLs are often analog in nature and take a very long time to simulate, and a design that works in one manufacturing process might stop working when manufactured using another process. Further, analog PLLs can be particularly sensitive to radiation. Hence, PLLS are very difficult to design, and often are not feasible in a given circuit or system.
Therefore, DLLs are often a preferred method of performing clock synchronization. However, the output signals provided by known DLLs can be “glitchy” or “noisy”, i.e., can pulse briefly high or low, during periods when the DLL is changing state. DLLs typically run continuously during the entire time the two clock signals must be synchronized, frequently adjusting the DLL output clock signal to keep the destination clock signal properly synchronized with the input clock signal. Hence, a glitchy output signal from a DLL can inject significant noise into the clock network served by the DLL.
Therefore, it is desirable to provide a DLL that provides a glitch-free output clock signal.